1. Field of the Invention
The present invention relates to a field of semiconductor integrated circuit (IC) manufacturing, and more specifically, to a device having and a method of forming a high-k dual dielectric stack.
2. Discussion of Related Art
An integrated circuit (IC) may include various active devices and passive devices. In particular, the IC may be designed using a complementary metal-oxide-semiconductor (CMOS) technology that includes an NMOS transistor and a PMOS transistor. Other devices, such as resistors, capacitors, and inductors, may also be included.
A scaling down of dimensions of the integrated circuit (IC) depends on a combination of technical and economic factors. For over 40 years, Moore's Law has accurately tracked a doubling in density of the IC every 18 months.
The transistors may be fabricated in a substrate on a wafer. The substrate may be formed from a semiconductor material, such as Silicon. The transistors have a gate dielectric film. The gate dielectric film may be formed from an oxidation of the Silicon or by deposition of a dielectric on the Silicon. The oxidation may be performed thermally. The resultant gate oxide, such as SiO2, has a dielectric constant, k, with a value of 3.9.
Scaling down each succeeding generation of the IC requires a reduction in channel length and gate dielectric film thickness. However, leakage current will also become larger.
In particular, a need exists for a gate dielectric film that is formed from a material with a higher value of k than the SiO2.
The advancement of Moore's law may require other materials to replace Silicon. However, the formation of high-k dielectric directly on Group III-V semiconductors may result in pinning of a Fermi-level at a surface.